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DS2153Q E1 Single-Chip Transceiver
www.dalsemi.com
FEATURES
Complete E1(CEPT) PCM-30/ISDN-PRI transceiver functionality Onboard line interface for clock/data recovery and waveshaping 32-bit or 128-bit jitter attenuator Generates line build-outs for both 120-ohm and 75-ohm lines Frames to FAS, CAS, and CRC4 formats Dual onboard two-frame elastic store slip buffers that can connect to backplanes up to 8.192 MHz 8-bit parallel control port that can be used on either multiplexed or non-multiplexed buses Extracts and inserts CAS signaling Detects and generates Remote and AIS alarms Programmable output clocks for Fractional E1, H0, and H12 applications Fully independent transmit and receive functionality Full access to both Si and Sa bits Three separate loopbacks for testing Large counters for bipolar and code violations, CRC4 code word errors, FAS errors, and E bits Pin-compatible with DS2151Q T1 SingleChip Transceiver 5V supply; low power CMOS Industrial grade version (-40C to +85C) available (DS2153QN)
PIN ASSIGNMENT
FUNCTIONAL BLOCKS
LONG & SHORT HAUL LINE INTERFACE
PARALLEL CONTROL PORT
DALLAS DS2153Q E1 SCT
ACTUAL SIZE OF 44-PIN PLCC CS RD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 TCHCLK
6 5 4 3 2 1 44 43 42 41 18 19 20 21 22 23 24 25 26 27
FRAMER
DESCRIPTION
The DS2153Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection to E1 lines. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial stream. The DS2153 automatically adjusts to E1 22 AWG (0.6 mm) twisted-pair cables from 0 to 1.5 km. The device can generate the necessary G.703 waveshapes for both 75-ohm and 120-ohm cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a set of 71 8-bit internal registers which the user can access to control the operation 1 of 52 070299
RCHBLK ACLKI BTS RTIP RRING RVDD RVSS XTAL1 XTAL2 INT1 INT2
28
ALE WR RLINK RLCLK DVSS RCLK RCHCLK RSER RSYNC RLOS/LOTC SYSCLK
40
ELASTIC STORES
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
TSER TCLK DVDD TSYNC TLINK TLCLK TCHBLK TRING TVDD TVSS TTIP
DS2153Q
of the unit. Quick access via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all of the latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011, 300 233, TBR 12 and TBR 13.
TABLE OF CONTENTS
1. Introduction 2. Parallel Control Port 3. Control and Test Registers 4. Status and Information Registers 5. Error Count Registers 6. Sa Data Link Control and Operation 7. Signaling Operation 8. Transmit Idle Registers 9. Clock Blocking Registers 10. Elastic Store Operation 11. Additional (Sa) and International (Si) Bit Operation 12. Line Interface Control Function 13. Timing Diagrams, Synchronization Flowchart, and Transmit flow Diagram 14. DC and AC Characteristics
1.0 INTRODUCTION
The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the SYSCLK input. The transmit side of the DS2153Q is totally independent from the receive side in both the clock requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP and TRING pins via a coupling transformer.
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DS2153Q
Reader's Note
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit timeslots in E1 systems which are numbered 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: FAS CAS MF Si CRC4 CCS Sa E-bit Frame Alignment Signal Channel Associated Signaling Multiframe International Bits Cyclical Redundancy Check Common Channel Signaling Additional bits CRC4 Error bits
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DS2153Q
DS2153Q BLOCK DIAGRAM Figure 1-1
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DS2153Q
PIN DESCRIPTION Table 1-1
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 SYMBOL AD4 AD5 AD6 AD7
RD (DS)
CS
TYPE I/O
DESCRIPTION Address/Data Bus. An 8-bit multiplexed address/data bus.
I I I I O O O O
Read Input (Data Strobe). Chip Select. Must be low to read or write the port. Address Latch Enable (Address Strobe). A positive going edge serves to demultiplex the bus. Write Input (Read/Write). Receive Link Data. Outputs the full receive data stream including the Sa bits. See Section 13 for timing details. Receive Link Clock. 4 kHz to 20 kHz demand clock for the RLINK output; controlled by RCR2. See Section 13 for timing details. Digital Signal Ground. 0.0 volts. Should be tied to local ground plane. Receive Clock. Recovered 2.048 MHz clock. Receive Channel Clock. 256 kHz clock which pulses high during the LSB of each channel. Useful for parallel to serial conversion of channel data. See Section 13 for timing details. Receive Serial Data. Received NRZ serial data, updated on rising edges of RCLK or SYSCLK. Receive Sync. An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR1.6=0) or multiframe boundaries (RCR1.6=1). If the elastic store is enabled via the RCR2.1, then this pin can be enabled to be an input via RCR1.5 at which a frame boundary pulse is applied. See Section 13 for timing details. Receive Loss of Sync/Loss of Transmit Clock. A dual function output. If TCR2.0=0, will toggle high when the synchronizer is searching for the E1 frame and multiframe; if TCR2.0=1, will toggle high if the TCLK pin has not toggled for 5 s. System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store functions are enabled via RCR2.1. Should be tied low in applications that do not use the elastic store. If tied high for at least 100 s, will force all output pins (including the parallel port) to 3-state.
ALE(AS)
WR (R/ W )
RLINK RLCLK DVSS RCLK RCHCLK
14 15
RSER RSYNC
O I/O
16
RLOS/LOTC
O
17
SYSCLK
I
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DS2153Q
PIN 18
SYMBOL RCHBLK
TYPE O
DESCRIPTION Receive Channel Block. A user-programmable output that can be forced high or low during any of the 32 E1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used, such as Fractional E1, 384 kbps service (H0), 1920 kbps (H12), or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications. See Section 13 for timing details. Alternate Clock Input. Upon a receive carrier loss, the clock applied at this pin (normally 2.048 MHz) will be routed to the RCLK pin. If no clock is routed to this pin, then it should be tied to DVSS VIA A 1 k resistor. Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins assume the function listed in parenthesis (). Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects to a 1:1 transformer (see Section 12 for details). Receive Analog Positive Supply. 5.0 volts. Should be tied to DVDD and TVDD pins. Receive Signal Ground. 0.0 volts. Should be tied to local ground plane. Crystal Connections. A pullable 8.192 MHz crystal must be applied to these pins. See Section 12 for crystal specifications. Receive Alarm Interrupt 1. Flags host controller during alarm conditions defined in Status Register 1. Active low, open drain output. Receive Alarm Interrupt 2. Flags host controller during conditions defined in Status Register 2. Active low, open drain output. Transmit Tip. Analog line driver output; connects to a step-up transformer (see Section 12 for details). Transmit Signal Ground. 0.0 volts. Should be tied to local ground plane. Transmit Analog Positive Supply. 5.0 volts. Should be tied to DVDD and RVDD pins. Transmit Ring. Analog line driver outputs; connects to a step-up transformer (see Section 12 for details).
19
ACLKI
I
20
BTS
I
21 22 23 24 25 26 27
RTIP RRING RVDD RVSS XTAL1 XTAL2
INT1
O
28 29 30 31 32
INT2
O -
TTIP TVSS TVDD TRING
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DS2153Q
PIN 33
SYMBOL TCHBLK
TYPE O
DESCRIPTION Transmit Channel Block. A user-programmable output that can be forced high or low during any of the 32 E1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used, such as Fractional E1, 384 kbps service (H0), 1920 kbps (H12), or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications. See Section 13 for timing details. Transmit Link Clock. 4 kHz to 20 kHz demand clock for the TLINK input; controlled by TCR2. See Section 13 for timing details. Transmit Link Data. If enabled, this pin will be sampled on the falling edge of TCLK to insert the Sa bits See Section 13 for timing details. Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q can be programmed to output either a frame or multiframe pulse at this pin. See Section 13 for timing details. Digital Positive Supply. 5.0 volts. Should be tied to RVDD and TVDD pins. Transmit Clock. 2.048 MHz primary clock. Needed for proper operation of the parallel control port. Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge of TCLK. Transmit Channel Clock. 256 kHz clock which pulses high during the LSB of each channel. Useful for parallel to serial conversion of channel data. See Section 13 for timing details. Address/Data Bus. A 8-bit multiplexed address/data bus.
34
TLCLK
O
35
TLINK
I
36
TSYNC
I/O
37 38 39 40
DVDD TCLK TSER TCHCLK
I I O
41 42 43 44
AD0 AD1 AD2 AD3
I/O
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DS2153Q REGISTER MAP
ADDRESS R/W 00 01 02 03 04 05 06 07 08 10 11 12 13 14 15 16 17 18 19 1A 1B 1E 1F R R R R R R R R REGISTER NAME BPV or Code Violation Count 1 BPV or Code Violation Count 2 CRC4 Count 1/FAS Error Count 1 CRC4 Error Count 2 E-Bit Count 1/FAS Error Count 2 E-Bit Count 2 Status 1 Status 2 ADDRESS 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2E 2E 2F R/W REGISTER NAME R/W Transmit Align Frame R/W Transmit Non-Align Frame R/W Transmit Channel Blocking 1 R/W Transmit Channel Blocking 2 R/W Transmit Channel Blocking 3 R/W Transmit Channel Blocking 4 R/W Transmit Idle 1 R/W Transmit Idle 2 R/W Transmit Idle 3 R/W Transmit Idle 4 R/W Transmit Idle Definition R/W Receive Channel Blocking 1 R/W Receive Channel Blocking 2 R/W Receive Channel Blocking 3 R/W Receive Channel Blocking 4 R Receive Align Frame
R/W Receive Information R/W Receive Control 1 R/W Receive Control 2 R/W Transmit Control 1 R/W Transmit Control 2 R/W Common Control 1 R/W Test 1 R/W Interrupt Mask 1 R/W Interrupt Mask 2 R/W Line Interface Control R/W Test 2 R/W Common Control 2 R/W Common Control 3 R R Synchronizer Status Receive Non-Align Frame
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ADDRESS R/W 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E R R R R R R R R R R R R R R R
REGISTER NAME Receive Signaling 1 Receive Signaling 2 Receive Signaling 3 Receive Signaling 4 Receive Signaling 5 Receive Signaling 6 Receive Signaling 7 Receive Signaling 8 Receive Signaling 9 Receive Signaling 10 Receive Signaling 11 Receive Signaling 12 Receive Signaling 13 Receive Signaling 14 Receive Signaling 15
ADDRESS 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
R/W
REGISTER NAME
R/W Transmit Signaling 1 R/W Transmit Signaling 2 R/W Transmit Signaling 3 R/W Transmit Signaling 4 R/W Transmit Signaling 5 R/W Transmit Signaling 6 R/W Transmit Signaling 7 R/W Transmit Signaling 8 R/W Transmit Signaling 9 R/W Transmit Signaling 10 R/W Transmit Signaling 11 R/W Transmit Signaling 12 R/W Transmit Signaling 13 R/W Transmit Signaling 14 R/W Transmit Signaling 15
3F R Receive Signaling 16 4F R/W Transmit Signaling 16 Note: the Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to insure proper operation.
2.0 PARALLEL PORT
The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the AC Electrical Characteristics for more details. The multiplexed bus on the DS2153Q saves pins because the address information and data information share the same signal paths. The addresses are presented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2153Q latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS WR pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing.
3.0 CONTROL AND TEST REGISTERS
The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and three Common Control Registers (CCR1, CCR2 and CCR3). Each of the seven registers are described in this section. The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On powerup, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly. 9 of 52
DS2153Q
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB) RSMF RSM RSIO POSITION RCR1.7 FRC SYNCE (LSB) RESYNC
SYMBOL RSMF
NAME AND DESCRIPTION RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the multiframe mode (RCR1.6=1). 0=RSYNC outputs CAS multiframe boundaries 1=RSYNC outputs CRC4 multiframe boundaries RSYNC Mode Select. 0=frame mode (see the timing in Section 13) 1=multiframe mode (see the timing in Section 13) RSYNC I/O Select. 0=RSYNC is an output (depends on RCR1.6) 1=RSYNC is an input (only valid if elastic store enabled) (note: this bit must be set to 0 when RCR2.1=0) Not Assigned. Should be set to 0 when written. Not Assigned. Should be set to 0 when written. Frame Resync Criteria. 0=resync if FAS received in error 3 consecutive times 1=resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times Sync Enable. 0=auto resync enabled 1=auto resync disabled Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.
RSM
RCR1.6
RSIO
RCR1.5
FRC
RCR1.4 RCR1.3 RCR1.2
SYNCE
RCR1.1
RESYNC
RCR1.0
SYNC/RESYNC CRITERIA Table 3-1
FRAME OR MULTIFRAME LEVEL
FAS
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS present in frames N and N + 2, and Three consecutive incorrect FAS G.706 FAS not present in frame N + 1. received. 4.1.1 4.1.2 Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non-FAS received.
CRC4
Two valid MF alignment words found 915 or more CRC4 code words out G.706 within 8 ms. of 1000 received in error. 4.2 4.3.2 Valid MF alignment word found and Two consecutive MF alignment previous time slot 16 contains code words received in error. other than all 0s. G.732 5.2
CAS
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DS2153Q
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB) Sa8S Sa7S Sa6S POSITION RCR2.7 RCR2.6 Sa5S Sa4S RSCLKM RESE (LSB) -
SYMBOL Sa8S Sa7S
NAME AND DESCRIPTION Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin; set to 0 to not report the Sa8 bit. Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin; set to 0 to not report the Sa7 bit. Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin; set to 0 to not report the Sa6 bit. Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin; set to 0 to not report the Sa5 bit. Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin; set to 0 to not report the Sa4 bit. Receive Side SYSCLK Mode Select. 0=if SYSCLK is 1.544 MHz 1=if SYSCLK is 2.048 MHz Receive Side Elastic Store Enable. 0=elastic store is bypassed 1=elastic store is enabled Not Assigned. Should be set to 0 when written.
Sa6S Sa5S
RCR2.5 RCR2.4
Sa4S RSCLKM
RCR2.3 RCR2.2
RESE
RCR2.1
-
RCR2.0
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DS2153Q
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB) TFPT T16S POSITION TCR1.7 TCR1.6 TUA1 TSiS TSA1 TSM (LSB) TSIO
SYMBOL TFPT
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Transmit Timeslot 0 Pass Through. 0=FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1=FAS bits/Sa bits/Remote Alarm sourced from TSER Transmit Timeslot 16 Data Select. 0=sample timeslot 16 at TSER pin 1=source timeslot 16 from TS1 to TS16 registers Transmit Unframed All 1s. 0=transmit data normally 1=transmit an unframed all 1's code at TPOS and TNEG Transmit International Bit Select. 0=sample Si bits at TSER pin 1=source Si bits from TAF and TNAF registers (in this mode, TCR1.6 must be set to 0) Transmit Signaling All 1s. 0=normal operation 1=force timeslot 16 in every frame to all 1s TSYNC Mode Select. 0=frame mode (see the timing in Section 13) 1=CAS and CRC4 multiframe mode (see the timing in Section 13) TSYNC I/O Select. 0=TSYNC is an input 1=TSYNC is an output
T16S
TCR1.5
TUA1
TCR1.4
TSiS
TCR1.3
TSA1
TCR1.2
TSM
TCR1.1
TSIO
TCR1.0
Note: See Figure 13-9 for more details about how the Transmit Control Registers affect the operation of the DS2153Q.
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DS2153Q
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)
(MSB) Sa8S Sa7S Sa6S POSITION TCR2.7 TCR2.6 Sa5S Sa4S AEBE (LSB) P16F
SYMBOL Sa8S Sa7S
NAME AND DESCRIPTION Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK pin; set to 0 to not source the Sa8 bit. Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK pin; set to 0 to not source the Sa7 bit. Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK pin; set to 0 to not source the Sa6 bit. Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK pin; set to 0 to not source the Sa5 bit. Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK pin; set to 0 to not source the Sa4 bit. Not Assigned. Should be set to 0 when written. Automatic E-Bit Enable. 0=E-bits not automatically set in the transmit direction 1=E-bits automatically set in the transmit direction Function of Pin 16. 0=Receive Loss of Sync (RLOS) 1=Loss of Transmit Clock (LOTC)
Sa6S Sa5S
TCR2.5 TCR2.4
Sa4S AEBE
TCR2.3 TCR2.2 TCR2.1
P16F
TCR2.0
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DS2153Q
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB) FLB THDB3 TG802 POSITION CCR1.7 TCRC4 RSM RHDB3 RG802 (LSB) RCRC4
SYMBOL FLB
NAME AND DESCRIPTION Framer Loopback. 0=loopback disabled 1=loopback enabled Transmit HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Transmit G.802 Enable. See Section 13 for details. 0=do not force TCHBLK high during bit 1 of timeslot 26 1=force TCHBLK high during bit 1 of timeslot 26 Transmit CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled Receive Signaling Mode Select. 0=CAS signaling mode 1=CCS signaling mode Receive HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Receive G.802 Enable. See Section 13 for details. 0=do not force RCHBLK high during bit 1 of timeslot 26 1=force RCHBLK high during bit 1 of timeslot 26 Receive CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled
THDB3
CCR1.6
TG802
CCR1.5
TCRC4
CCR1.4
RSM
CCR1.3
RHDB3
CCR1.2
RG802
CCR1.1
RCRC4
CCR1.0
FRAMER LOOPBACK
When CCR1.7 is set to a 1, the DS2153Q will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1. data will be transmitted as normal at TTIP and TRING 2. data off the E1 line at RTIP and RRING will be ignored 3. the RCLK output will be replaced with the TCLK input.
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DS2153Q
CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)
(MSB) ECUS VCRFS AAIS POSITION CCR2.7 ARA RSERC LOTCMC RLB (LSB) LLB
SYMBOL ECUS
NAME AND DESCRIPTION Error Counter Update Select. 0=update error counters once a second 1=update error counters every 62.5 ms (500 frames) VCR Function Select. 0=count BiPolar Violations (BPVs) 1=count Code Violations (CVs) Automatic AIS Generation. 0=disabled 1=enabled Automatic Remote Alarm Generation. 0=disabled 1=enabled RSER Control. 0=allow RSER to output data as received under all conditions 1=force RSER to 1 under loss of frame alignment conditions Loss of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to the ever present RCLK if the TCLK should fail to transition (see Figure 1.1). 0=do not switch to RCLK if TCLK stops 1=switch to RCLK if TCLK stops Remote Loopback. 0=loopback disabled 1=loopback enabled Local Loopback. 0=loopback disabled 1=loopback enabled
VCRFS
CCR2.6
AAIS
CCR2.5
ARA
CCR2.4
RSERC
CCR2.3
LOTCMC
CCR2.2
RLB
CCR2.1
LLB
CCR2.0
REMOTE LOOPBACK
When CCR2.1 is set to a 1, the DS2153Q will be forced into Remote LoopBack (RLB). In this loopback, data recovered off of the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line (with any BPV's that might have occurred intact) via the TTIP and TRING pins. Data will continue to pass through the receive side of the DS2153Q as it would normally and the data at the TSER pin will be ignored. Data in this loopback will pass through the jitter attenuator. Please see Figure 1.1 for more details.
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DS2153Q
LOCAL LOOPBACK
When CCR2.0 is set to a 1, the DS2153Q will be forced into Local LoopBack (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. Please see Figure 1.1 for more details.
AUTOMATIC ALARM GENERATION
When either CCR2.4 or CCR2.5 is set to 1, the DS2153Q monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the DS2151Q will either force an AIS alarm (if CCR2.5=1) or a Remote Alarm (CCR2.4=1) to be transmitted via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1 at the same time.
CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
(MSB) TESE TCBFS TIRFS POSITION CCR3.7 ESR LIRST TSCLKM (LSB) -
SYMBOL TESE
NAME AND DESCRIPTION Transmit Elastic Store Enable. 0 = elastic store is disabled 1 = elastic store is enabled Transmit Channel Blocking Registers (TCBR) Function Select. 0=TCBRs define the operation of the TCHBLK output pin 1=TCBRs define which signaling bits are to be inserted Transmit Idle Registers (TIR) Function Select. 0=TIRs define in which channels to insert idle code 1=TIRs define in which channels to insert data from RSER Elastic Stores Reset. Setting this bit from a 1 to a 0 will force the elastic stores to a known depth. Should be toggled after SYSCLK has been applied and is stable. Must be set and cleared again for a subsequent reset. Do not leave this bit set high. Line Interface Reset. Setting this bit from a 0 to a 1 will initiate an internal reset that affects the slicer, AGC, clock recovery state machine, and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Not Assigned. Should be set to 0 when written. Transmit Backplane Clock Select. Must be set like RCR2.2. 0 = 1.544 MHz 1 = 2.048 MHz Not Assigned. Should be set to 0 when written.
TCBFS
CCR3.6
TIRFS
CCR3.5
ESR
CCR3.4
LIRST
CCR3.3
TSCLKM
CCR3.2 CCR3.1
-
CCR3.0
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POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS2153Q should be configured for operation by writing to all of the internal registers (this includes the Test Registers) since the contents of the internal registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to reset the line interface circuitry (it will take the DS2153Q about 40 ms to recover from the LIRST bit being toggled). Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 and back to 0 (this step can be skipped if the elastic store is not being used).
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS2153Q, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion (except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again or if the alarm is still present. The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register will be updated with current value and it will be cleared. When a 0 is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2153Q with higher-order software languages. The SSR register operates differently than the other three. It is a read-only register and it reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write. The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2 pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2) respectively.
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RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB) TESF TESE JALT POSITION RIR.7 RIR.6 RESF RESE CRCRC FASRC (LSB) CASRC
SYMBOL TESF TESE
NAME AND DESCRIPTION Transmit Elastic Store Full. Set when the elastic store fills and a frame is deleted. Transmit Elastic Store Empty. Set when the elastic store empties and a frame is repeated. Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4-bits of its limit; useful for debugging jitter attenuation operation. Elastic Store Full. Set when the elastic store buffer fills and a frame is deleted. Elastic Store Empty. Set when the elastic store buffer empties and a frame is repeated. CRC Resync Criteria Met. Set when 915/1000 code words are received in error. FAS Resync Criteria Met. Set when three consecutive FAS words are received in error. CAS Resync Criteria Met. Set when two consecutive CAS MF alignment words are received in error.
JALT
RIR.5
RESF RESE
RIR.4 RIR.3
CRCRC FASRC
RIR.2 RIR.1
CASRC
RIR.0
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SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB) CSC5 CSC4 CSC3 POSITION SSR.7 SSR.6 SSR.5 SSR.4 SSR.3 CSC2 CSC0 FASSA CASSA (LSB) CRC4SA
SYMBOL CSC5 CSC4 CSC3 CSC2 CSC0
NAME AND DESCRIPTION CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CRC4 Sync Counter Bit 4. CRC4 Sync Counter Bit 3. CRC4 Sync Counter Bit 2. CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next to LSB bit is not accessible. This bit will toggle each time the CRC4 MF search times out at 8 ms. FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word.
FASSA CASSA
SSR.2 SSR.1
CRC4SA
SSR.0
CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter is cleared when the DS2153Q has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter will rollover.
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SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB) RSA1 RDMA RSA0 POSITION SR1.7 RSLIP RUA1 RRA RCL (LSB) RLOS
SYMBOL RSA1
NAME AND DESCRIPTION Receive Signaling All 1s. Set when the contents of timeslot 16 contains less than three 0s over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Receive Distant MF Alarm. Set when bit 6 of timeslot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. Receive Signaling All 0s. Set when over a full MF, timeslot 16 contains all 0s. Receive Elastic Store Slip Occurrence. Set when the elastic store has either repeated or deleted a frame of data. Receive Unframed All 1s. Set when an unframed all 1s code is received at RTIP and RRING. Receive Remote Alarm. Set when a remote alarm is received at RTIP and RRING. Receive Carrier Loss. Set when 255 consecutive 0s have been detected at RTIP and RRING. Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream.
RDMA
SR1.6
RSA0 RSLIP
SR1.5 SR1.4
RUA1 RRA
SR1.3 SR1.2
RCL RLOS
SR1.1 SR1.0
ALARM CRITERIA Table 4-1
ALARM
RSA1 (receive signaling all 1s) RSA0 (receive signaling all 0s) RDMA (receive distant multiframe alarm) RUA1 (receive unframed all 1s)
SET CRITERIA
CLEAR CRITERIA
CCITT SPEC.
over 16 consecutive frames (one full over 16 consecutive frames (one G.732 MF) timeslot 16 contains less than three full MF) timeslot 16 contains three 4.2 0s or more 0s over 16 consecutive frames (one full over 16 consecutive frames (one G.732 full MF) timeslot 16 contains at 5.2 MF) timeslot 16 contains all 0s least a single 1 bit 6 in timeslot 16 of frame 0 set to 1 for two consecutive MF bit 6 in timeslot 16 of frame 0 set to O.162 0 for a two consecutive MF 2.1.5
less than three 0s in two frames (512 more than two 0s in two frames O.162 bits) (512 bits) 1.6.1.2
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RRA (receive remote alarm) RCL (receive carrier loss)
bit 3 of non-align frame set to 1 for three bit 3 of non-align frame set to 0 for O.162 consecutive occasions three consecutive occasions 2.1.4 255 consecutive 0s received in 255-bit times, at least 32 1s are G.775 received
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB) RMF RAF TMF POSITION SR2.7 SEC TAF LOTC RCMF (LSB) TSLIP
SYMBOL RMF
NAME AND DESCRIPTION Receive CAS Multiframe. Set every 2 ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available. Receive Align Frame. Set every 250 ms at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Transmit Multiframe. Set every 2 s (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. 1-Second Timer. Set on increments of 1 second based on RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms instead of once a second. Transmit Align Frame. Set every 250 s at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 3.9 s). Will force pin 16 high if enabled via TCR2.0. Based on RCLK. Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if CRC4 is disabled. Transmit Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data.
RAF
SR2.6
TMF
SR2.5
SEC
SR2.4
TAF
SR2.3
LOTC
SR2.2
RCMF
SR2.1
TSLIP
SR2.0
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IMR1: INTERRUPT MASK REGISTER1 (Address=16 Hex)
(MSB) RSA1 RDMA RSA0 POSITION IMR1.7 RSLIP RUA1 RRA RCL (LSB) RLOS
SYMBOL RSA1
NAME AND DESCRIPTION Receive Signaling All 1s. 0=interrupt masked 1=interrupt enabled Receive Distant MF Alarm. 0=interrupt masked 1=interrupt enabled Receive Signaling All 0s. 0=interrupt masked 1=interrupt enabled Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All 1s. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled
RDMA
IMR1.6
RSA0
IMR1.5
RSLIP
IMR1.4
RUA1
IMR1.3
RRA
IMR1.2
RCL
IMR1.1
RLOS
IMR1.0
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IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB) RMF RAF TMF POSITION IMR2.7 SEC TAF LOTC RCMF (LSB) TSLIP
SYMBOL RMF
NAME AND DESCRIPTION Receive CAS Multiframe. 0=interrupt masked 1=interrupt enabled Receive Align Frame. 0=interrupt masked 1=interrupt enabled Transmit Multiframe. 0=interrupt masked 1=interrupt enabled 1-Second Timer. 0=interrupt masked 1=interrupt enabled Transmit Align Frame. 0=interrupt masked 1=interrupt enabled Loss Of Transmit Clock. 0=interrupt masked 1=interrupt enabled Receive CRC4 Multiframe. 0=interrupt masked 1=interrupt enabled Transmit Side Elastic Store Slip. 0 = interrupt masked 1 = interrupt enabled
RAF
IMR2.6
TMF
IMR2.5
SEC
IMR2.4
TAF
IMR2.3
LOTC
IMR2.2
RCMF
IMR2.1
TSLIP
IMR2.0
5.0 ERROR COUNT REGISTERS
There are a set of four counters in the DS2153Q that record bipolar or code violations, errors in the CRC4 SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four counters are automatically updated on either 1-second boundaries (CCR2.7=0) or every 62.5 ms (CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt from the timer to determine when to read these registers. The user has a full second (or 62.5 ms) to read the counters before the data is lost.
5.1 BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0, 23 of 52
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then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in CCITT O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the DS2153Q should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10**-2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex) VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB) V15 V7 V14 V6 SYMBOL V15 V0 V13 V5 POSITION VCR1.7 VCR2.0 V12 V4 V11 V3 V10 V2 V9 V1 (LSB) V8 V0 VCR1 VCR2
NAME AND DESCRIPTION MSB of the 16-bit bipolar or code violation count LSB of the 16-bit bipolar or code violation count
5.2 CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex) CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB) (note 1) CRC7 (note 1) CRC6 (note 1) CRC5 POSITION CRCCR1.1 CRCCR2.0 (note 1) CRC4 (note 1) CRC3 (note 1) CRC2 CRC9 CRC1 (LSB) CRC8 CRCCR1 CRC0 CRCCR2
SYMBOL CRC9 CRC0
NAME AND DESCRIPTION MSB of the 10-bit CRC4 error count LSB of the 10-bit CRC4 error count
NOTES:
1. The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error counter.
5.3 E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15 24 of 52
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on E1 lines running with CRC4 multiframe. These count registers will increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
EBCR1: E-BIT COUNT REGISTER 1 (Address=04 Hex) EBCR2: E-BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB) (note 1) EB7 (note 1) EB6 SYMBOL EB9 EB0 (note 1) EB5 POSITION EBCR1.1 EBCR2.0 (note 1) EB4 (note 1) EB3 (note 1) EB2 EB9 EB1 (LSB) EB8 EB0 EBCR1 EBCR2
NAME AND DESCRIPTION MSB of the 10-bit E-Bit count LSB of the 10-bit E-Bit count
NOTES:
1. The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
5.4 FAS Bit Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12-bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is disabled during loss of synchronization conditions, (RLOS = 1). Since the maximum FAS word error count in a 1-second period is 4000, this counter cannot saturate.
FASCR1: FAS BIT COUNT REGISTER 1 (Address=02 Hex) FASCR2: FAS BIT COUNT REGISTER 2 (Address=04 Hex)
(MSB) FAS11 FAS5 FAS10 FAS4 FAS9 FAS3 POSITION FASCR1.7 FASCR2.2 FAS8 FAS2 FAS7 FAS1 FAS6 FAS0 (note 2) (note 1) (LSB) (note 2) (note 1) FASCR1 FASCR2
SYMBOL FAS11 FAS0
NAME AND DESCRIPTION MSB of the 12-bit FAS error count LSB of the 12-bit FAS error count
NOTES:
1. The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error counter. 2. The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-Bit counter.
6.0 Sa DATA LINK CONTROL AND OPERATION
The DS2153Q provides for access to the proposed E1 performance monitor data link in the Sa bit positions. The device allows access to the Sa bits either via a set of two internal registers (RNAF and TNAF) or via two external pins (RLINK and TLINK). 25 of 52
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On the receive side, the Sa bits are always reported in the internal RNAF register (see Section 11 for more details). All five Sa bits are always output at the RLINK pin. See Section 13 for detailed timing. Via RCR2, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can be used to capture the needed Sa bits. On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (TCR1.6=0) or from the external TLINK pin. Via TCR2, the DS2153Q can be programmed to source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits through the DS2153Q without them being altered, then the device should be set up to source all five Sa bits via the TLINK pin and the TLINK pin should be tied to the TSER pin. Please see the timing diagrams and the transmit data flow diagram in Section 13 for examples.
7.0 SIGNALING OPERATION
The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2153Q. Each of the 30 channels has four signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the channel associated with a particular signaling bit. The channel numbers have been assigned as described in the ITU documents. For example, channel 1 is associated with timeslot 1 and channel 30 is associated with timeslot 31. There is a set of 16 registers for the receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to TS16). The signaling registers are detailed below.
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RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex)
(MSB) 0 A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) 0 B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10) B(11) B(12) B(13) B(14) B(15) 0 C(1) C(2) C(3) C(4) C(5) C(6) C(7) C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15) POSITION RS1.0/1/3 RS1.2 RS2.7 RS16.0 0 D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) X A(16) A(17) A(18) A(19) A(20) A(21) A(22) A(23) A(24) A(25) A(26) A(27) A(28) A(29) A(30) Y B(16) B(17) B(18) B(19) B(20) B(21) B(22) B(23) B(24) B(25) B(26) B(27) B(28) B(29) B(30) X C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23) C(24) C(25) C(26) C(27) C(28) C(29) C(30) (LSB) X D(16) D(17) D(18) D(19) D(20) D(21) D(22) D(23) D(24) D(25) D(26) D(27) D(28) D(29) D(30) RS1 (30) RS2 (31) RS3 (32) RS4 (33) RS5 (34) RS6 (35) RS7 (33) RS8 (37) RS9 (38) RS10 (39) RS11 (3A) RS12 (3B) RS13 (3C) RS14 (3D) RS15 (3E) RS16 (3F)
SYMBOL X Y A(1) D(30)
NAME AND DESCRIPTION Spare Bits Remote Alarm Bit (integrated and reported in SR1.6) Signaling Bit A for Channel 1 Signaling Bit D for Channel 30
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The user has a full 2 ms to retrieve the signaling bits before the data is lost. The RS registers are updated under all conditions. Their validity should be qualified by checking for synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been loaded with data. The user has 2 ms to retrieve the data before it is lost.
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TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex)
(MSB) 0 A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) 0 B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10) B(11) B(12) B(13) B(14) B(15) 0 C(1) C(2) C(3) C(4) C(5) C(6) C(7) C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15) POSITION TS1.0/1/3 TS1.2 TS2.7 TS16.0 0 D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) X A(31) A(32) A(33) A(34) A(35) A(36) A(37) A(38) A(39) A(40) A(41) A(42) A(43) A(44) A(45) Y B(16) B(17) B(18) B(19) B(20) B(21) B(22) B(23) B(24) B(25) B(26) B(27) B(28) B(29) B(30) X C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23) C(24) C(25) C(26) C(27) C(28) C(29) C(30) (LSB) X D(16) D(17) D(18) D(19) D(20) D(21) D(22) D(23) D(24) D(25) D(26) D(27) D(28) D(29) D(30) TS1 (40) TS2 (41) TS3 (42) TS4 (43) TS5 (44) TS6 (45) TS7 (43) TS8 (47) TS9 (48) TS10 (49) TS11 (4A) TS12 (4B) TS13 (4C) TS14 (4D) TS15 (43) TS16 (4F)
SYMBOL X Y A(1) D(30)
NAME AND DESCRIPTION Spare Bits Remote Alarm Bit Signaling Bit A for Channel 1 Signaling Bit D for Channel 30
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the DS2153Q will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2.5) to know when to update the signaling bits. The bit will be set every 2 ms and the user has 2 ms to update the TSRs before the old data will be retransmitted. The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble. The upper nibble must always be set to 0000, or else the terminal at the far end will lose multiframe synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit should be set to a 1. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three remaining bits in TS1 are the spare bits. If they are not used, they should be set to 1. In CCS signaling mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be informed when the signaling registers need to be loaded with data. The user has 2 ms to load the data before the old data will be retransmitted. Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) to determine on a channel by channel basis which signaling bits are 28 of 52
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to be inserted via the TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from the TSER pin (the corresponding bit in the TCBRs=0). See the Transmit Data Flow diagram in Section 13 for more details.
8.0 TRANSMIT IDLE REGISTERS
There is a set of five registers in the DS2153Q that can be used to custom tailor the data that is to be transmitted onto the E1 line, on a channel by channel basis. Each of the 32 E1 channels can be forced to have a user defined idle code inserted into them.
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
(MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 SYMBOL CH32 CH6 CH14 CH22 CH30 POSITION TIR4.7 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 TIR1 (26) TIR2 (27) TIR3 (28) TIR4 (29)
NAME AND DESCRIPTION Transmit Idle Registers. 0=do not insert the Idle Code into this channel 1=insert the Idle Code into this channel
CH1
TIR1.0
NOTE:
If CCR3.5=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be sourced from the RSER pin.
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB) TIDR7 TIDR6 TIDR5 POSITION TIDR.7 TIDR.0 TIDR4 TIDR3 TIDR2 TIDR1 (LSB) TIDR0
SYMBOL TIDR7 TIDR0
NAME AND DESCRIPTION MSB of the Idle Code LSB of the Idle Code
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a timeslot in the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). In the TIDR, the MSB is transmitted first. Via the CCR3.5 bit, the user has the option to use the TIRs to determine on a channel by channel basis, if data from the RSER pin should be substituted for data from the TSER pin. In this mode, if the corresponding bit in the TIRs is set to 1, then data will be sourced from the RSER pin. If the corresponding bit in the TIRs is set to 0, then data for that channel will sourced from the TSER pin. See the Transmit Data Flow diagram in Section 13 for more details.
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9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section 13 for an example. The TCBRs have an alternate mode of use. Via the CCR3.6 bit, the user has the option to use the TCBRs to determine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from the TSER pin (the corresponding bit in the TCBR=0). See the Transmit Data Flow diagram in Section 13 for more details.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS (Address=2B to 2E Hex)
(MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 SYMBOL CH32 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RCBR1 (2B) RCBR2 (2C) RCBR3 (2D) RCBR4 (2E)
POSITION RCBR4.7
NAME AND DESCRIPTION Receive Channel Blocking Registers. 0=force the RCHBLK pin to remain low during this channel time 1=force the RCHBLK pin high during this channel time
CH1
RCBR1.0
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS (Address=22 to 25 Hex)
(MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 SYMBOL CH32 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 TCBR1 (22) TCBR2 (23) TCBR3 (24) TCBR4 (25)
POSITION TCBR4.7
NAME AND DESCRIPTION Transmit Channel Blocking Registers. 0=force the TCHBLK pin to remain low during this channel time 1=force the TCHBLK pin high during this channel time
CH1
TCBR1.0
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NOTE:
If CCR3.6=1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER and a 1 implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS) registers. See definition below.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1
(MSB) CH20 CH24 CH28 CH32 CH4 CH8 CH12 CH16 CH19 CH23 CH27 CH31 CH3 CH7 CH11 CH15 CH18 CH22 CH26 CH30 CH2 CH6 CH10 CH14 CH17* CH21 CH25 CH29 (LSB) CH1* CH5 CH9 CH13 TCBR1 TCBR2 TCBR3 TCBR4
* = CH1 and CH17 should be set to 1 to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits.
10.0 ELASTIC STORE OPERATION
The DS2153Q has an onboard two-frame (512 bits) elastic store. This elastic store can be enabled via RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz (RCR2.2=0) or 2.048 MHz (RCR2.2=1) clock at the SYSCLK pin. If the elastic store is enabled, then the user has the option of either providing a frame sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame boundary, then RCR1.6 must be set to 0, and if the user wishes to have pulses occur at the multiframe boundary, then RCR1.6 must be set to 1. If the user selects to apply a 1.544 MHz clock to the SYSCLK pin, then every fourth channel will be deleted and the F-bit position inserted (forced to 1). Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted. Also, in 1.544 MHz applications, the RCHBLK output will not be active in channels 25 through 32 (or in other words, RCBR4 is not active). See Section 13 for more details. If the 512-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.
11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS2153Q provides for access to both the Additional (Sa) and International (Si) bits. On the receive side, the RAF and RNAF registers will always report the data as it received in the Additional and International bit locations. The RAF and RNAF registers are updated with the setting of the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers. It has 250 s to retrieve the data before it is lost. On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the TAF and TNAF registers. It has 250 s to update the data or else the old data will be retransmitted. Data in the Si bit position will be overwritten if either the DS2153Q is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1. Please see the register descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 13 for more details.
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RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)
(MSB) Si 0 0 POSITION RAF.7 RAF.6 RAF.5 RAF.4 RAF.3 RAF.2 RAF.1 RAF.0 1 1 0 1 (LSB) 1
SYMBOL Si 0 0 1 1 0 1 1
NAME AND DESCRIPTION International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit.
RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address=1F Hex)
(MSB) Si 1 A POSITION RNAF.7 RNAF.6 RNAF.5 RNAF.4 RNAF.3 RNAF.2 RNAF.1 RNAF.0 Sa4 Sa5 Sa6 Sa7 (LSB) Sa8
SYMBOL Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8.
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TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex)
(MSB) Si 0 0 POSITION TAF.7 TAF.6 TAF.5 TAF.4 TAF.3 TAF.2 TAF.1 TAF.0 1 1 0 1 (LSB) 1
SYMBOL Si 0 0 1 1 0 1 1
NAME AND DESCRIPTION International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit.
TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address=21 Hex)
(MSB) Si 1 A POSITION TNAF.7 TNAF.6 TNAF.5 TNAF.4 TNAF.3 TNAF.2 TNAF.1 TNAF.0 Sa4 Sa5 Sa6 Sa7 (LSB) Sa8
SYMBOL Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8.
12.0 LINE INTERFACE FUNCTIONS
The line interface function in the DS2153Q contains three sections: (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR), which is described below. 33 of 52
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LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex)
(MSB) L2 L1 L0 POSITION LICR.7 LICR.6 EGL JAS JABDS DJA (LSB) TPD LICR
SYMBOL LB2 LB1
NAME AND DESCRIPTION Line Build Out Bit 2. Transmit waveshape setting; see Table 12.2. Line Build Out Bit 1. Transmit waveshape setting; see Table 12.2. Line Build Out Bit 0. Transmit waveshape setting; see Table 12.2. Receive Equalizer Gain Limit. 0 = -12 dB 1 = -30 dB Jitter Attenuator Select. 0=place the jitter attenuator on the receive side 1=place the jitter attenuator on the transmit side Jitter Attenuator Buffer Depth Select . 0=128 bits 1=32 bits (use for delay sensitive applications) Disable Jitter Attenuator. 0=jitter attenuator enabled 1=jitter attenuator disabled Transmit Power Down. 0=normal transmitter operation 1=powers down the transmitter and 3-states the TTIP and TRING pins
LB0 EGL
LICR.5 LICR.4
JAS
LICR.3
JABDS
LICR.2
DJA
LICR.1
TPD
LICR.0
12.1 Receive Clock and Data Recovery
The DS2153Q contains a digital clock recovery system. See the DS2153Q Block Diagram in Section 1 and Figure 12.1 for more details. The DS2153Q couples to the receive E1 shielded twisted pair or COAX via a 1:1 transformer. See Table 12.3 for transformer details. The DS2153Q automatically adjusts to the E1 signal being received at the RTIP and RRING pins and can handle E1 twisted pair cables of 0.6 mm (22 AWG) from 0 to 1.5 KM in length. The crystal attached at the XTAL1 and XTAL2 pins is multiplied by 4 via an internal PLL and fed to the clock recovery system. The clock recovery system uses both edges of the clock from the PLL circuit to form a 32 times oversampler which is used to recover the clock and data. This oversampling technique offers outstanding jitter tolerance (see Figure 12.2). Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI 34 of 52
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pin or from the crystal attached to the XTAL1 and XTAL2 pins. The DS2153Q will sense the ACLKI pin to determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to RVSS to prevent the device from falsely sensing a clock. See Table 12.1. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the Receive AC Timing Characteristics in Section 14 for more details.
SOURCE OF RCLK UPON RCL Table 12-1
ACLKI PRESENT? yes no RECEIVE SIDE JITTER ATTENUATOR ACLKI via the jitter attenuator centered crystal TRANSMIT SIDE JITTER ATTENUATOR ACLKI TCLK via the jitter attenuator
12.2 Transmit Waveshaping and Line Driving
The DS2153Q uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms created by the DS2153Q meet the ITU specifications. See Figure 12.3. The user will select which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR). The DS2153Q can set up in a number of various configurations depending on the application. See Table 12.2 and Figure 12.1.
LINE BUILD OUT SELECT IN LICR Table 12-2
L2 0 0 0 0 1 1 L1 0 0 1 1 0 1 L0 0 1 0 1 0 0 APPLICATION 75-ohm normal 120-ohm normal 75-ohm normal with protection resistors 120-ohm normal with protection resistors 75-ohm with high return loss 75-ohm with high return loss TRANSFORMER 1:1.15 step-up 1:1.15 step-up 1:1.15 step-up 1:1.15 step-up 1:1.15 step-up 1:1.36 step-up 1:1.36 step-up RETURN LOSS NM NM NM NM 21 dB 21 dB 21 dB Rt 0 ohms 0 ohms 8.2 ohms 8.2 ohms 27 ohms 18 ohms 27 ohms
1 0 0 120-ohm with high return loss NM=Not Meaningful
Due to the nature of the design of the transmitter in the DS2153Q, very little jitter (less then 0.00 5UIpp broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLK. Also, the waveforms that they create are independent of the duty cycle of TCLK. The transmitter in the DS2153Q couples to the E1 transmit shielded twisted pair or COAX via a 1:1.15 or 1:1.36 step up transformer as shown in Figure 12.1. In order for the devices to create the proper waveforms, this transformer used must meet the specifications listed in Table 12.3.
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TRANSFORMER SPECIFICATIONS Table 12-3
SPECIFICATION Turns Ratio Primary Inductance Leakage Inductance Interwinding Capacitance DC Resistance RECOMMENDED VALUE 1:1 (receive) and 1:1.15 or 1:1.36 (transmit) 5% 600 H minimum 1.0 H maximum 60 pF maximum 1.2 ohms maximum
12.3 Jitter Attenuator
The DS2153Q contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in Figure 12.4. The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 12.4 below must be connected to the XTAL1 and XTAL2 pins. The jitter attenuator divides the clock provided by the 8.192 MHz crystal at the XTAL1 and XTAL2 pins to create an output clock that contains very little jitter. Onboard circuitry will pull the crystal (by switching in or out load capacitance) to keep it long-term averaged to the same frequency as the incoming E1 signal. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the normal 4 to keep the buffer from overflowing. When the device divides by either 3.5 or 4.5, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
CRYSTAL SPECIFICATIONS GUIDELINES Table 12-4
PARAMETER Parallel Resonant Frequency Mode Load Capacitance Tolerance Pullability Effective Series Resistance Crystal Cut 8.192 MHz Fundamental 18 pF to 20 pF (18.5 pF nominal) 50 ppm CL=10 pF, delta frequency=+175 to +250 ppm CL=45 pF, delta frequency=-175 to -250 ppm 30 ohms maximum AT SPECIFICATION
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DS2153Q EXTERNAL ANALOG CONNECTIONS Figure 12-1
NOTES:
1. All resistor values are 1%. 2. The Rt resistors are used to increase the transmitter return loss or to protect the device from overvoltage. 3. The Rr resistors are used to terminate the receive E1 line. 4. For 75-ohm termination, Rr=37.5 ohms/for 12- ohm termination Rr=60 ohms. 5. See the separate Application Note for details on how to construct a protected interface.
DS2153Q JITTER TOLERANCE Figure 12-2
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DS2153Q TRANSMIT WAVEFORM TEMPLATE Figure 12-3
DS2153Q JITTER ATTENUATION Figure 12-4
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13.0 TIMING DIAGRAMS/SYNCHRONIZATION FLOWCHART/TRANSMIT DATA FLOW DIAGRAM RECEIVE SIDE TIMING Figure 13-1
NOTES:
1. RSYNC in the frame mode (RCR1.6=0). 2. RSYNC in the multiframe mode (RCR1.6=1). 3. RLCLK is programmed to output just the Sa4 bit. 4. RLINK will always output all five Sa bits as well as the rest of the receive data stream. 5. This diagram assumes the CAS MF begins with the FAS word.
RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORES DISABLED) Figure 13-2
NOTES:
1. RCHBLK is programmed to block channel 2. 2. RLINK is programmed to output the Sa4 bits. 3. RLINK is programmed to output the SA4 and SA8 bits. 4. RLINK is programmed to output the Sa5 and Sa7 bits. 5. Shown is a non-align frame boundary. 39 of 52
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1.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13-3
NOTES:
1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to 1). 2. RSYNC is in the output mode (RCR1.5=0). 3. RSYNC is in the input mode (RCR1.5=1). 4. RCHBLK is programmed to block channel 24.
2.048 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13-4
NOTES:
1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). 3. RCHBLK is programmed to block channel 1.
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TRANSMIT SIDE TIMING Figure 13-5
NOTES:
1. TSYNC in the frame mode (TCR1.1=0). 2. TSYNC in the multiframe mode (TCR1.1=1). 3. TLINK is programmed to source only the Sa4 bit. 4. This diagram assembles both the CAS MF and the CRC4 begin with the align frame.
TRANSMIT SIDE BOUNDARY TIMING Figure 13-6
NOTES:
1. TSYNC is in the input mode (TCR1.0=0). 2. TSYNC is in the output mode (TCR1.0=1). 3. TCHBLK is programmed to block channel 2. 4. TLINK is programmed to source the Sa4 bits. 5. TLINK is programmed to source the Sa7 and Sa8 bits. 6. Shown is a non-align frame boundary. 7. See Figures 13.3 and 13.4 for details on timing with the transmit side elastic store enabled. 41 of 52
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G.802 TIMING Figure 13-7
NOTE:
1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 1 to 15, 17 to 25, and during bit 1 of timeslot 26.
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DS2153Q SYNCHRONIZATION FLOWCHART Figure 13-8
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DS2153Q TRANSMIT DATA FLOW Figure 13-9
NOTE:
1. TCLK must be tied to RCLK (or SYSCLK if the elastic store is enabled) and TSYNC must be tied to RSYNC for data to be properly sourced from RSER.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -1.0V to +7.0V 0C to 70C (-40C to +85C for DS2153QN) -55C to +125C 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATION CONDITIONS
PARAMETER Logic 1 Logic 0 Supply for DS2153Q Supply for DS2153QN SYMBOL VIH VIL VDD VDD
(0C to 70C) (-40C to +85C for DS2153QN)
MIN 2.0 -0.3 4.75 4.80 TYP MAX VDD+0.3 +0.8 5.25 5.25 UNITS V V V V 1 1 NOTES
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 5 7 MAX
(tA=25C)
UNITS pF pF NOTES
DC CHARACTERISTICS
PARAMETER Supply Current @ 5V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V)
(0C to 70C; VDD=5V 5%) (-40C to +85C; VDD=5V +5%/-4% for DS2153QN)
SYMBOL IDD IIL ILO IOH IOL -1.0 +4.0 MIN -1.0 TYP 60 MAX +1.0 1.0 UNITS mA A A mA mA NOTES 2 3 4
NOTES:
1. Applies to RVDD, TVDD, and DVDD. 2. TCLK=2.048 MHz. 3. 0.0V < VIN < VDD. 4. Applies to INT1 and INT2 when 3-stated.
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AC CHARACTERISTICS (0C to 70C; VDD=5V 5%) PARALLEL PORT (-40C to +85C; VDD=5V +5%/-4% for DS2153QN)
PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Time R/ W Hold Time R/ W Setup Time Before DS High
CS Setup Time Before DS, WR or RD
SYMBOL tCYC PWEL PWEH tR, tF tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW
MIN 250 150 100
TYP
MAX
UNITS ns ns ns
NOTES
30 10 50 20 0 10 0 20 10 25 40 20 20 80 100 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
active
CS Hold Time
Read Data Hold Time Write Data Hold Time Muxed Address Valid to AS or ALE fall Muxed Address Hold Time Delay Time DS, WR or RD to AS or ALE Rise Pulse Width AS or ALE High Delay Time, AS or ALE to DS, WR or
RD
Output Data Delay Time from DS or
RD
Data Setup Time
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INTEL READ BUS AC TIMING Figure 14-1
INTEL WRITE BUS AC TIMING Figure 14-2
MOTOROLA BUS AC TIMING Figure 14-3
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AC CHARACTERISTICS (0C to 70C; VDD=5V 5%) RECEIVE SIDE (-40C to +85C; VDD =5V +5%/-4% for DS2153QN)
PARAMETER ACLKI/RCLK Period RCLK Pulse Width RCLK Pulse Width SYSCLK Period SYSCLK Pulse Width RSYNC Set Up to SYSCLK Falling RSYNC Pulse Width SYSCLK Rise/Fall Times Delay RCLK or SYSCLK to RSER Valid Delay RCLK or SYSCLK to RCHCLK Delay RCLK or SYSCLK to RCHBLK Delay RCLK or SYSCLK to RSYNC Delay RCLK to RLCLK Delay RCLK to RLINK Valid SYMBOL tCP tCH tCL tCH tCL tSP tSP tSH tSL tSU tPW tR, tF tDD tD1 tD2 tD3 tD4 tD5 50 50 25 50 25 70 50 50 50 50 50 tSH-5 MIN 180 180 90 200 TYP 488 244 244 244 244 648 488 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 1 2 3 4
NOTES:
1. Jitter attenuator enabled in the receive side path. 2. Jitter attenuator disabled or enabled in the transmit path. 3. SYSCLK=1.544 MHz. 4. SYSCLK=2.048 MHz.
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RECEIVE SIDE AC TIMING Figure 14-4
NOTES:
1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). 3. RLCLK and RLINK only have a timing relationship to RCLK; no timing relationship between RLCLK/RLINK and RSYNC is implied. 4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path.
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AC CHARACTERISTICS (0C to 70C; VDD=5V 5%) TRANSMIT SIDE (-40C to +85C; VDD=5V +5%/-4% for DS2153QN)
PARAMETER TCLK Period TCLK Pulse Width TSER, TLINK Set Up to TCLK Falling TSER, TLINK Hold from TCLK Falling TSYNC Setup to TCLK Falling TSYNC Pulse Width TCLK Rise/Fall Times Delay TCLK to TCHCLK Delay TCLK to TCHBLK Delay TCLK to TSYNC Delay TCLK to TLCLK SYMBOL tP tCH tCL tSU tHD tHD tPW tR, tF tD1 tD2 tD3 tD4 MIN 75 75 25 25 25 25 25 50 50 50 50 tCH-5 TYP 488 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns 1 1 NOTES
NOTES:
1. If the transmit side elastic store is enabled, then TSER is sampled on the falling edge of SYSCLK and the parameters tSU and tHD still apply.
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TRANSMIT SIDE AC TIMING Figure 14-5
NOTES:
1. TSYNC is in the output mode (TCR1.0=1). 2. TSYNC is in the input mode (TCR1.0=0). 3. No timing relationship between TSYNC and TLCLK/TLINK is implied. 4. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled.
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DS2153Q E1 SINGLE-CHIP TRANSCEIVER 44-PIN PLCC
NOTE 1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. INCHES DIM A A1 A2 B B1 C CH1 D D1 D2 E E1 E2 e1 N MIN 0.165 0.090 0.020 0.026 0.013 0.009 0.042 0.685 0.650 0.590 0.685 0.650 0.590 MAX 0.180 0.120 0.033 0.021 0.012 0.048 0.695 0.656 0.630 0.695 0.656 0.630
0.050 BSC 44 -
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